Micro-gap Filling for TSV Package and Simple Underfill Process for TSV Stacking
Micro-gap Filling for TSV Package and Simple Underfill Process for TSV Stacking
For stacking TSV (Through Silicon Via) chips different interconnection methods exist which result in leaving small gaps (5~15 µm) between the stacked chips (Figure 1). Due to the smallness of the gaps it is difficult to use conventional flip-chip underfill material and technology. If a CUF (Capillary Underfill) process is utilized, long processing time is introduced if several dies are to be stacked, because after each process cure time is needed (cf. Figure 1). For instance, if a four-fold stack is to be stacked, after the first die is attached to the substrate, the underfill material can be pasted. The second die is then bonded under thermo compression. The underfill is cured and the procedures are repeated for the other dies. This, however, introduces thermal stress to all layers and materials, having a bad impact on package quality. A state of the art stair configuration with several same-sized dies without underfill process is depicted in Figure 2.
