Selecting an underfill for flip chip packaging
Reliability concerns in flip chip packaging pivot on the underfill material used, apart from other factors. Hinge your selection of the right underfill on its properties such as CTE, viscosity, flow characteristics, modulus, and adhesion.
By Dr. Ignatius J. Rasiah Material Scientist Johnson Matthey (Singapore)
As IC packages clock higher frequencies and pin counts, assembly houses are considering flip chip packaging to meet high volume demands. The underfill material used in this process in no small way determines the reliability of the package, irrespective of its nonmolded or overmolded design.
Matching the CTE
Among the material properties, the coefficient of thermal expansion (CTE) of the underfill should match that of the solder bump connecting thedie to the substrate. Typical solders used for flip chip are Pb5Sn (with a CTE of 29ppm) and eutectic solder (with a CTE of 24.3ppm). Thus, formulating an underfill calls for fine tuning the material to have a CTE
within this range. The CTE of an underfill is adjusted by varying two parameters, the silica filler and the polymer hemistry of the material. The optimum filler loading is in the range of 60 to 65 percent for the two types of solders,
and varies somewhat with other filter properties such as particle size……
download pdf file:
Selecting an underfill for flip chip packaging (243.2 KB, 2 次)
您没有权限下载此文件。
